Display apparatus

ABSTRACT

Amplifier circuits (AMPi, AMPj) are provided corresponding to data lines (DLi, DLj) arranged corresponding to columns of display pixels (PX). In the amplifier circuit, a non-inversion input of a differential amplifier circuit ( 32 ) is connected to the corresponding data line, and an inversion input node (N 2 ) is connected to a capacitance element ( 34 ). Before pixel data of a displaying pixel element is read onto the data line, the non-inversion input of the differential amplifier circuit is precharged to a predetermined voltage level, and an output node of the differential amplifier circuit is coupled to the inversion input node (N 2 ). The differential amplifier circuit operates as a voltage follower, and the capacitance element stores a comparison reference voltage including information corresponding to an offset of the differential amplifier circuit. Thereafter, data of the displaying pixel element is read onto the data line, and is amplified by the amplifier circuit so that the pixel data can be accurately amplified while canceling the offset of the differential amplifier circuit.

This application is a 371 of PCT/JP02/10633 Oct. 11, 2002

TECHNICAL FIELD

The present invention relates to a display device for displaying images,and particularly to a display device that drives displaying pixelelements arranged corresponding to pixels by a voltage held by acapacitance.

BACKGROUND ART

LCDs (Liquid Crystal Displays) have been known as one type of displaydevices. In particular, a liquid crystal display of a thin filmtransistor driven type (TFT-LCDs), which uses Thin Film Transistors(TFTs) for selecting displaying pixel elements, have been known as onetype of LCDs. In the thin film transistor, an amorphous silicon (a-Si)semiconductor thin film or a polycrystalline silicon (p-Si)semiconductor thin film is used as a base material (active layer), and achannel portion and source/drain portions are formed in the activelayer.

In a liquid crystal panel of an active matrix type, TFTs serving asswitches for image signals are provided for the displaying pixelelements, and through switching operations of these TFTs, drive voltagesof the displaying pixel elements are held. Thus, the active matrix typeliquid crystal panel are excellent in image quality such as contrast,and response speeds, and therefore are widely used as monitors for apersonal computer of portable type and desktop type as well as aprojection monitor for displaying still and motion pictures.

In each of pixels of the display device of the active matrix type, adata-holding capacitance element (capacitance element for holding data)holds an image signal applied via the TFT. The displaying pixel elementis driven in accordance with the voltage held by the capacitanceelement.

In the display device, displaying pixels are arranged in rows andcolumns, and gate lines (scanning lines) are arranged corresponding tothe respective rows of the pixels. By sequentially driving the scanninglines to the selected state, the TFTs connected to a selected gate lineare turned on so that the image signals are transferred to and held inthe corresponding data-holding capacitance elements. As a sequence ofdriving the gate lines (scanning lines), there are an interlace systemof sequentially driving alternate scanning lines to the selected stateand a non-interlace system of sequentially driving the successive gatelines to the selected state. In any of these driving systems, for eachpixel, there is required a time period in which all the gate lines(scanning lines) are once driven to the selected state after an imagesignal is once written before a next image signal is written into. Anentire of the gate lines (scanning lines) forms one frame. Therefore,each displaying pixel element is required to hold the received imagesignal by the data-holding capacitance element for duration of one frameperiod. Usually, one frame cycle (frame frequency) is provided by 60hertz (Hz). Therefore, rewriting of the holding voltage is performed ineach unit pixel element for each one-frame period PF (= 1/60 second).During this frame period of time, the voltage on a pixel electrode node(voltage holding node) lowers only slightly, so that a change inreflectance (luminance) of the liquid crystal element of the pixel issmall, and flicker, reduction in contrast and reduction in displayquality are sufficiently suppressed.

In the liquid crystal display device, the current is mainly consumed forcharging and discharging capacitances at crossings between scanninglines and data signal lines as well as capacitances of liquid crystalbetween the interconnection lines (scanning lines and data signal lines)and counter electrodes formed on a whole surface of the opposingsubstrate. A vertical scanning circuit driving the scanning lines to theselected state operates at a frequency equal to (framefrequency)×(number of scanning lines). Also, a horizontal scanningcircuit writing image signal data onto data signal lines operates at afrequency equal to (frame frequency)×(number of scanning lines)×(numberof data signal lines). Accordingly, charging and discharging of theinter-line capacitances as well as the capacitances between theinterconnecting lines and the counter electrodes are performed at theoperation frequencies of these vertical scanning circuit and thehorizontal scanning circuit so that power consumption is increased.

For reducing the power consumption, it may be effective to lower theoperation frequency, or to perform intermittently the vertical scanningand horizontal scanning. However, if the operation frequencies of thehorizontal and vertical scanning circuits are lowered, a data rewritingperiod increases, and the voltage lowering at the pixel electrode node(voltage holding node) due to a leakage current significantly becomeslarge so that a reflectance (luminance) of the displaying pixel elementaccordingly changes significantly. Therefore, the voltage lowering ofthe pixel electrode node is observed as a flicker on a display screen,which degrades the display image quality. In addition, an averagevoltage applied to the liquid crystal element lowers so that goodcontrast cannot be achieved. Further, a display response speed lowersdue to slow rewriting. These factors result in degraded display quality.

Japanese Patent Laying-Open No. 2000-356974 discloses an arrangement forpreventing the voltage lowering due to the leakage current at the pixelelectrode nodes of the display pixels, in which cross coupled type senseamplifiers formed of MOS transistors (insulated-gate field-effecttransistors) are provided corresponding to the respective data lines towrite inverted output signals of the output signals of the senseamplifiers into original displaying pixel elements.

In this prior art, when only holding of data is to be performed, thegate lines are sequentially selected to read pixel electrode signals ofdisplay pixels into the sense amplifiers, and inverted data of the senseamplifiers are re-stored on electrode nodes of original pixel elements.In the device in which the displaying pixel elements are formed ofliquid crystal elements, storage of inverted image signals is performedfor holding the image signals by application of AC voltages to theliquid crystal layers.

This prior art intends to reduce the power dissipation by restoring theheld voltages of the respective pixel internally to eliminate thenecessity for writing data from an external memory to restore (refresh)the accumulated voltages of the displaying pixel elements.

In the display device, for MOS transistors (insulated-gate field-effecttransistors), generally low-temperature polycrystalline silicon TFTs areemployed for ensuring reliability of a glass substrate or an insulatingresin substrate for forming pixels. For the low-temperaturepolycrystalline silicon TFTs, impurity diffusion and other processes areperformed through low-temperature processing. As compared with bulk typeMOS transistors formed on a surface of a semiconductor substrate region,therefore, impurity diffusion is not sufficient, and a film quality ofthe polycrystalline silicon is low either. Further, the gate insulatingfilm is not heat-processed or annealed at a sufficiently hightemperature so that the film quality thereof is low. In the case of theTFT, a channel region is formed of a semiconductor layer formed on aglass substrate or an insulating resin substrate, and implantation ofimpurity ions for controlling a threshold voltage is not performed.Further, no bias voltage is applied to the substrate region.

For these factors, variations in threshold voltage of TFTs in displaydevices are larger than in bulk type MOS transistors. In the structureemploying sense amplifier circuits for restoring (refreshing) the heldvoltage of the pixels, the sense amplifiers are arranged correspondingto the display pixel matrix, and therefore, it is required to uselow-temperature TFTs for the components of the sense amplifier circuits.Such sense amplifier circuits accompany the problem that variations inthreshold voltage of the TFTs are large and therefore accurate sensingoperation cannot be achieved. Specifically, such sense amplifier circuitis formed of cross-coupled TFTs, and input signals undergo offset whenthe cross-coupled TFTs have different threshold voltages, so that thesense amplifier circuit cannot accurately amplify the data.

In particular, the held voltage in the pixel is merely held by adata-holding capacitance element in the pixel element, and a readvoltage to the sense amplifier circuit is small. Therefore, when theinput signals undergo the offset due to large variation in thresholdvoltages as described above, the sense amplifier circuit cannotaccurately amplify the pixel voltage read from the pixel element, andthe held voltage of the pixel cannot be refreshed.

Japanese Patent Laying-Open Nos. 20001-292041 and H9-320291 disclose thestructures for reducing an offset in an operational amplifier of asample/hold circuit arranged at an output of a horizontal drive circuitdriving data lines in image display devices. These prior arts disclosethe arrangements for reducing an adverse influence by the offset of theoperational amplifier to incoming image signal, in which an outputsignal of the operational amplifier is fed back to bias a comparisonreference voltage to cancel the offset of the operational amplifier. Inthese prior arts, however, consideration is given only to aconfiguration of a data line drive circuit for writing data into pixelsin accordance with image data, and no consideration is given to such aproblem of the lowering of held voltages in the pixels due to leakagecurrent.

In addition, a test must be performed for determining whether each pixelcan accurately perform a display operation after completion of themanufacturing process. In testing, test pixel data is written into eachpixel, and then the pixel data thus written are read externally forcomparison with the test data. In this test, it is therefore necessaryto amplify accurately a minute voltage read from the pixel and to readthe amplified voltage externally. For this, a tester is required todetect the minute pixel voltage, and thus becomes expensive.

DISCLOSURE OF THE INVENTION

An object of the invention is to provide a display device, which canaccurately hold a pixel data voltage.

Another object of the invention is to provide a display device, whichcan easily perform a test of pixels with an inexpensive tester.

A display device according to the invention includes a plurality ofdisplaying pixel elements arranged in rows and columns; a plurality ofgate lines, arranged corresponding to the respective display pixel rows,each connected to the displaying pixel elements in a corresponding rowfor selecting the displaying pixels in the corresponding row whenselected; a plurality of data lines, arranged corresponding to therespective display pixel columns, each connected to the displaying pixelelements in a corresponding column for transferring pixel data to thedisplaying pixel elements in the corresponding column; and a pluralityof amplifier circuits, arranged corresponding to the respective pixelcolumns, each amplifying the data on the data line in a correspondingcolumn when activated. Each amplifier circuit includes a capacitanceelement, a differential amplifier circuit having a first input coupledto the corresponding data line and a second input connected to thecapacitance element for differentially amplifying signals on the firstand second input signals when activated, a first switching elementcoupling the first input to a reference power supply supplying apredetermined voltage in response to an operation mode instructingsignal, and a second switching element coupling an output of thedifferential amplifier circuit to the capacitance element in response tothe operation mode instructing signal.

The amplifier circuit is arranged for each data line. In the amplifiercircuit, the first input of the differential amplifier circuit iscoupled to the predetermined power supply, and the second input iscoupled to the capacitance receiving the output signal. Thereby, thecapacitance element stores an offset voltage of the reference voltage.When a pixel is selected and the pixel data is transferred to thedifferential amplifier circuit, the pixel data can be differentiallyamplified while canceling the offset in the differential amplifiercircuit. Therefore, even when large variations occur in thresholdvoltage of TFTs of the differential amplifier circuit, the image datacan be accurately restored without an influence of the offset due tosuch variations in threshold voltage.

By writing the output signal of the differential amplifier circuit intothe original pixel, the pixel data can be refreshed (restored). Byreading externally the output signal of the differential amplifiercircuit, a data signal of a large amplitude can be read externally, andit is not necessary to externally amplify pixel data of a smallamplitude. Thus, a structure of a tester can be simplified, and thedisplay device can be easily tested with an inexpensive tester.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically shows a whole structure of a display deviceaccording to the invention.

FIG. 2 shows an example of a structure of a displaying pixel elementshown in FIG. 1.

FIG. 3 specifically shows a structure of a main portion of the displaydevice shown in FIG. 1.

FIG. 4 is a timing chart illustrating an operation of the structureshown in FIG. 3.

FIG. 5 schematically shows a structure of a vertical scanning circuitshown in FIG. 1.

FIG. 6 is a timing chart illustrating an operation of the verticalscanning circuit shown in FIG. 5.

FIG. 7 shows more specifically the operation of the vertical scanningcircuit shown in FIG. 5.

FIG. 8 is a timing chart illustrating operations of structures shown inFIGS. 3 and 5.

FIG. 9 schematically shows a structure of a portion for generatingcontrol signals related to a refresh operation.

FIG. 10 is a timing chart illustrating an operation of the circuitryshown in FIG. 9.

FIG. 11 shows an example of a structure of a portion for generatingconnection control signals of a refresh control circuit shown in FIG. 1.

FIG. 12 is a timing chart illustrating an operations of the circuitryshown in FIG. 11.

FIG. 13 shows an example of a structure of a differential amplifiercircuit shown in FIG. 3.

FIG. 14 shows another structure of the differential amplifier circuitshown in FIG. 3.

FIG. 15 shows further another structure of the differential amplifiercircuit shown in FIG. 3.

FIG. 16 schematically shows a structure of a major portion of a displaydevice according to a second embodiment of the invention.

FIG. 17 is a signal waveform diagram representing an operation of adisplaying pixel element shown in FIG. 16 in data reading.

FIG. 18 schematically shows a sectional structure of a capacitanceelement shown in FIG. 16.

FIG. 19 schematically shows a structure of a portion for generating aboosted signal shown in FIG. 16.

FIG. 20 is a signal waveform diagram illustrating an operation of thecircuitry shown in FIG. 19.

FIG. 21 schematically shows a structure of a display device according toa third embodiment of the invention.

FIG. 22 shows a structure of a main portion of the display device shownin FIG. 21.

FIG. 23 shows, by way of example, structures of a refresh circuit and atest circuit shown in FIG. 21.

FIG. 24 specifically shows connection between an amplifier circuit and atest select gate shown in FIG. 23.

FIG. 25 schematically shows a structure of a portion for generatingcontrol signals shown in FIG. 24.

FIG. 26 is a timing chart illustrating an operation of the circuitryshown in FIG. 25.

FIG. 27 schematically shows a structure of a portion for generating testselect control signals shown in FIG. 23.

FIG. 28 is a timing chart illustrating an operation of the circuitryshown in FIG. 2.

FIG. 29 shows another structure of a displaying pixel element.

FIG. 30 shows still another structure of the displaying pixel element.

FIG. 31 shows a further structure of the displaying pixel element.

FIG. 32 schematically shows a structure of a main portion of a displaydevice according to a fourth embodiment of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment]

FIG. 1 schematically shows a whole structure of an image display deviceaccording to a first embodiment of the invention. In FIG. 1, an imagedisplay device includes a display pixel matrix 1 including a pluralityof pixel elements PX arranged in rows and columns, a vertical scanningcircuit 2 sequentially selecting the rows in display pixel matrix 1 inaccordance with a vertical scan signal (not shown), a horizontalscanning circuit 3 for producing a signal to select a column in displaypixel matrix 1 in accordance with a horizontal clock signal (not shown),a data line connecting circuit 4 for sequentially transmitting imagedata PD to the columns in display pixel matrix 1 in accordance with theselect signal received from horizontal scanning circuit 3, a refreshcircuit 5 for refreshing a held voltage of each display pixel in displaypixel matrix 1 when made active, and a refresh control circuit 6 forcontrolling operations of vertical scanning circuit 2, data lineconnecting circuit 4 and refresh circuit 5 in accordance with a refreshmode instructing signal SELF.

In display pixel matrix 1, gate lines GL are arranged corresponding tothe respective rows of pixel elements PX, and data lines DL are arrangedcorresponding to the respective columns of pixel elements PX. Gate lineGL is connected to pixel elements PX on a row, and data line DL isconnected to pixel elements PX on a column. FIG. 1 representativelyshows pixel element PX arranged at a crossing between one gate line GLand one data line DL.

Vertical scanning circuit 2 drives gate line GL to a selected state in apredetermined sequence in both of a normal operation mode for rewritingthe held voltages of pixel elements PXs and a refresh mode for restoringthe held voltages. The sequence for driving gate lines GL to theselected state by vertical scanning circuit 2 may be any of thenon-interlace system of sequentially driving the successive rows to theselected state and the interlace system of driving the alternate rows tothe selected state.

Horizontal scanning circuit 3 includes, for example, a horizontal shiftregister for producing a data line select timing signal through a shiftoperation in accordance with a horizontal clock signal (not shown), anda buffer circuit for sequentially selecting data lines DLs in accordancewith the output signal of the horizontal shift register. Owing to theprovision of the buffer circuit in horizontal scanning circuit 3, it ispossible to prevent a multi-selection, in which a next data line isdriven to the selected state before a data line under selection transitsto the non-selected state.

In the normal operation, data line connecting circuit 4 sequentiallyselects the data lines in accordance with the output signal ofhorizontal scanning circuit 3, and transmit image data PD transmittedvia an image data bus (a common image data line) to the selectedcorresponding column in display pixel matrix 1. In the refresh mode,data line connecting circuit 4 is kept in cut off state to isolate theimage data bus (or data line driver) transmitting image data PD fromdisplay pixel matrix 1.

Data line connecting circuit 4 may be configured to takes in image dataPD for one row under control of horizontal scanning circuit 3, and thentransfers the one row image data concurrently to displaying pixelelements PX in the selected row of display pixel matrix 1. In thisconfiguration, a sample and hold circuit samples the image data, andthen transfers the sampled data concurrently.

When a refresh mode instructing signal SELF is active, refresh controlcircuit 6 activates the refresh circuit 5 to execute the refreshing(restoring) of the held voltage of each displaying pixel element PX indisplay pixel matrix 1. In the refresh mode, refresh control circuit 5may produce various clock signals required for the shift operation forvertical scanning circuit 2, or refresh control circuit 6 may producevarious clock signals required for the shift operation for verticalscanning circuit 2 in accordance with an externally applied clocksignal.

Refresh circuit 5 includes amplifier circuits, provided corresponding tothe respective data lines DLs, each formed of TFTs. A circuit forcanceling an offset is provided for each amplifier circuit in refreshcircuit 5, to cancel the offset due to variation in threshold voltage ofTFTs. Data amplified by the amplifier circuit with the offset cancelingfunction in refresh circuit 5 is written into an original pixel elementPX to refresh the held voltage of pixel element PX in display pixelmatrix 1.

It is not necessary to further read the refresh data (data forrefreshing) stored in an external memory for writing into display pixelmatrix 1 for the purpose of refreshing, so that power consumption can bereduced. In the refresh circuit 5, the circuit for amplifying the pixeldata contains a construction for canceling the offset, and the minutevoltage read from a displaying pixel element PX can be accuratelyamplified and written into the original pixel element PX. Thus, the heldvoltage can be maintained for a long period of time when no displayimage is changed, and degradation in image quality of the displayedimage can be reliably prevented.

In a test mode, the image data amplified by the amplifier circuit inrefresh circuit 5 is externally transmitted. The image data of a largeamplitude can be produced and outputted externally, and the displayingpixel elements can be tested with an inexpensive tester directed toLSIs.

FIG. 2 shows an example of a structure of displaying pixel element PXshown in FIG. 1. In FIG. 2, displaying pixel element PX includes anN-channel MOS transistor (TFT) 11 made conductive in accordance with asignal potential on gate line GL, to electrically couples acorresponding data line DL to a pixel electrode node (voltage holdingnode) 10, a voltage holding capacitance element 12 holding the voltageon voltage holding node 10, and a liquid crystal display element 13disposed between voltage holding node 10 and a counter electrode.

Voltage holding capacitance element 12 has one electrode node coupled tovoltage holding node 10, and receives a common electrode voltage Vcom onthe other electrode node. Voltage holding capacitance element 12accumulates charges corresponding to a difference between commonelectrode voltage Vcom and a signal voltage applied via data line DL aswell as a capacitance value of voltage holding capacitance element 12.

In liquid crystal display element 13, the orientation direction isdetermined by a voltage difference between the voltage on voltageholding node 10 and a counter electrode voltage Vcnt on the counterelectrode, and accordingly the reflectance (luminance) is determined.Counter electrode voltage Vcnt is placed over the whole area of displaypixel matrix 1. Common electrode voltage Vcom determines an amount ofaccumulated charges at voltage holding node 10, and is commonly appliedto each pixel element PX in display pixel matrix 1.

Charges held on voltage holding node 10 leak through liquid crystaldisplay element 13, capacitor 12 or TFT 11. The voltage held on thevoltage holding node 10 is restored to the original voltage levelthrough the refreshing operation by refresh circuit 5 shown in FIG. 1.Lowering of the voltage due to leakage of charges can be compensated forto maintain the image data accurately for a long period of time.

Usually, gate lines GL are driven between a high voltage and a negativevoltage. By driving gate lines GL to the high voltage level, the imagesignal transmitted onto data line DL can be transmitted to voltageholding node 10 without a loss of a threshold voltage of TFT 11. Bymaintaining gate line GL at the negative voltage level, TFT 11 is set toa deeply off state, and the leakage current through TFT 11 issuppressed.

FIG. 3 specifically shows structures of data line connecting circuit 4,display pixel matrix 1 and refresh circuit 5 shown in FIG. 1. FIG. 3representatively shows pixels PX arranged in two rows and two columns indisplay pixel matrix 1. Each of gate lines GLa and GLb is arranged forpixel elements PX aligned in one row, and each of data lines DLi and DLjis arranged for pixel elements PX aligned in one column. Gate lines GLaand GLb are supplied with gate line drive voltages VGa and VGb fromvertical scanning circuit 2 shown in FIG. 1, respectively.

Data line connecting circuit 4 includes data line select gates 20 i and20 j, which are selectively turned conductive in accordance with dataline select signals Hi and Hj applied from horizontal scanning circuit 3shown in FIG. 1, respectively, to transmit image data signal PD appliedfrom a common image data line 15, data line drivers 22 i and 22 jprovided corresponding data line select gates 20 i and 20 j,respectively, and isolation gates 24 i and 24 j arranged between outputsof data line drivers 22 i and 22 j and data lines DLi and DLj,respectively.

Isolation gates 24 i and 24 j selectively turn non-conductive inresponse to connection control signal S1, to isolate the outputs of dataline drivers 22 i and 22 j from data lines DLi and DLj, respectively. Inthe refresh mode, connection control signal S1 is made active to renderisolation gates 24 i and 24 j non-conductive.

Data line drivers 22 i and 22 j each are usually formed of a voltagefollowers, and produce a signal at a voltage level corresponding toimage data signal PD applied onto common data line 15 when correspondingdata line select gates 20 i and 20 j are conductive.

Refresh circuit 5 includes amplifier circuits AMPi and AMPi providedcorresponding to data lines DLi and DLj, respectively. In operation,amplifier circuits AMPi and AMPj differentially amplify the signals oncorresponding data lines DLi and DLj based on a comparison referencevoltage, and transmit the results of amplification onto correspondingdata lines DLi and DLj, respectively. Amplifier circuits AMPi and AMPjhave the same structure, and FIG. 3 representatively shows the structureof amplifier circuit AMPi provided for data line DLi.

Amplifier circuit AMPi includes a switching element 30 for transmittinga reference voltage VM to a node N1 in response to a switch controlsignal S2, a differential amplifier circuit 32 for differentiallyamplifying voltages on nodes N1 and N2, a switching element 33 forelectrically coupling an output node N3 of differential amplifiercircuit 32 to node N2 in accordance with switch control signal S2, acapacitance element 34 coupled between node N2 and a ground node,inverter buffers 35 and 36 cascaded in two stages and receiving theoutput signal of differential amplifier circuit 32, and a switchingelement 37 for transmitting an output signal of inverter buffer 36 todata line DLi in accordance with a switch control signal S4. Theseswitching elements 30, 33 and 37 are formed of transfer gates or CMOStransmission gates, and are formed of TFTs. Reference voltage VM issubstantially set to a value of (VH−VH)/2 intermediate the voltages VHand VL corresponding to H level data and L-level data of image signalswritten into pixel elements PX, respectively.

Differential amplifier circuit 32 has a non-inversion input connected tonode N1 and an inversion input connected to node N2. Therefore,differential amplifier circuit 32 amplifies the voltage on node N1 witha voltage on node N2 being a reference.

Inverter buffers 35 and 36 drive the corresponding data line DLi with alarge driving power in accordance with the output signal of differentialamplifier circuit 32. A refresh operation of the display device shown inFIG. 3 will now be described with reference to FIG. 4.

In accordance with activation of refresh mode instructing signal SELF,connection control signal S1 attains L level at a time t0, andresponsively, isolation gates 24 i and 24 j are turned non-conductive.In this state, the voltages VD on data lines DLi and DLj are in thefloating state, and gate line drive signals VG (VGa and VGb) on gatelines GLa and GLb are at the L level (the level of voltage VGL). In eachpixel element PX, therefore, all TFTs (11) are non-conductive, and theinternal voltage on the pixel electrode node is held by capacitanceelement 12.

After connection control signal S1 falls to the L level, switch controlsignals S2 and S3 are activated at a time t1, and switching elements 30and 33 turn conductive in amplifier circuits AMPi and AMPj,respectively. Responsively, data lines DLi and DLj indicated in genericby a reference character “DL” hereinafter) are each precharged to alevel of intermediate voltage VM via node N1.

In each of amplifier circuits AMPi and AMPj, differential amplifiercircuit 32 has the voltage level of output node N3 transmitted to nodeN2 via switching element 33. Thus, differential amplifier circuit 32 hasthe output connected to its own inversion input via switching element33, and operates as a voltage follower.

In differential amplifier circuit 32, an offset VOS is present due tovariation in threshold voltage of TFTs of its components. Therefore,differential amplifier circuit 32, of which output signal ideallyattains a level of the voltage VM on non-inversion input node N1,actually provides an output voltage of (VM+VOS) due to the offsetvoltage VOS. There is case in which the offset voltage VOS is a negativevoltage. FIG. 10 shows, as an example, a state in which offset voltageVOS is at a positive level, and output node N3 of differential amplifiercircuit 32 is at a voltage level higher than intermediate voltage VM.Node N2 is coupled to capacitance element 34, and therefore, capacitanceelement 34 holds the offset voltage information of differentialamplifier circuit 32.

When a predetermined time elapses, both switch control signals S2 and S3are made inactive at a time t2, and switching elements 30 and 33 turnnon-conductive. In this state, the voltage VD on data line DL is held atthe level of intermediate voltage VM by parasitic capacitance 27(generically representing 27 i and 27 j).

Capacitance element 34 holds the node N2 at the level of voltage of(VM+VOS). The voltage of (VM+VOS) is also maintained on output node N3of differential amplifier circuit 32. Differential amplifier circuit 32operates as a comparator for comparing the voltage on node N1, i.e., ondata line DL with the voltage on node N2 being a comparison referencevoltage. The comparison reference voltage held by capacitance element 34is set at a voltage of (VM+VOS) containing the offset voltage ofdifferential amplifier circuit 32. Therefore, differential amplifiercircuit 32 performs the comparing operation in the state in which theoffset is cancelled.

At a time t3, gate line GL (GLa or GLb) is driven to the selected state,and gate line drive signal VG (VGa or VGb) on the selected gate linerises to the H level (a voltage VGH level). The unselected gate line ismaintained at the L level (voltage VGL level). In pixel element PXconnected to selected gate line GL, the TFT turns conductive, andcharges held by voltage holding capacitance element 12 are transmittedto data line DL, so that data line voltage VD changes from theprecharged voltage VM. FIG. 4 illustrates a case, in which voltage VD ondata line DL further rises by a voltage of ΔVDH from intermediatevoltage VM set in the precharged state.

For the sake of simplicity, it is assumed that an image signal at Hlevel (voltage VH level) has written onto data line DL, the voltageholding node has no leakage current and no voltage lowering caused, andis maintained at the level of voltage VH. In this case, reading ofaccumulated charges from the pixel element causes, on data line DL, thevoltage change of ΔVDH, which is expressed by the following expression:ΔVDH=(VH−VM)·Cs/(Cd+Cs),where Cd and Cs represent a capacitance value of parasitic capacitance27 (27 i and 27 j) of the data line and a capacitance value ofcapacitance element 12 of the displaying pixel element, respectively.

Since VM is equal to (VH−VL)/2, the following expression (1) isobtained:ΔVDH=(VH−VL)·Cs/2·(Cd+Cs)  (1)

When the pixel element has stored the data signal at L level of voltageVL, the following expression is satisfied:

$\begin{matrix}\begin{matrix}{{\Delta\;{VDL}} = {\left( {{VL} - {VM}} \right) \cdot {{Cs}/2} \cdot \left( {{Cd} + {Cs}} \right)}} \\{= {\left( {{- {VH}} + {3 \cdot {VL}}} \right) \cdot {{Cs}/2} \cdot \left( {{Cd} + {Cs}} \right)}}\end{matrix} & (2)\end{matrix}$Assuming that VL is equal to 0 (V), the following expressions (3) and(4) are obtained.ΔVDH=VH·Cs/2·(Cd+Cs)  (3)ΔVDL=−VH·Cs/2·(Cd+Cs)  (4)Thus, a relationship of (ΔVDH=−ΔVDL) is obtained. A change amount involtage on the data line becomes the same between reading of the imagedata signal at the H level and reading of the image data signal at the Llevel.

Assuming that Cs/Cd=1/20 and VH=5 (V), the following representations areobtained:ΔVDH=2.5/20·1.1=0.119 (V)ΔVDL=−ΔVDH=−0.119 (V)

Thus, the voltage VD on data line DL ideally changes ±0.119 V aboutintermediate voltage VM (=2.5 V) in accordance with the data writteninto the pixel element. Differential amplifier circuit 32 amplifies thevoltage change ΔVDH or ΔVDL on the data line, and supplies a resultantsignal onto output node N3. Inverter buffers 35 and 36 transform theoutput signal of differential amplifier circuit 32 into a signal havinga larger driving power.

At a time t4, switch control signal S4 becomes active to renderswitching element 37 conductive. Responsively, data line DL is driven inaccordance with a voltage on a node N5 so that the voltage on data lineDL is driven up to the H level (voltage VH level). Voltage VD on dataline DL is written into original pixel element PX, and is held byvoltage holding capacitance element 12 because the corresponding gateline is in the selected state.

In amplifier circuits AMPi and AMPj, the operation power supply voltagesof inverters 36 are set to the levels of voltages VH and VLcorresponding to the H- and L levels of the pixel data signal,respectively, so that the written image data signal can be accuratelyrestored and rewritten into the original pixel, and the image data canbe refreshed.

In the comparing operation of differential amplifier circuit 32 startingat time t3, the voltage of (VM+ΔVDH) or (VM−ΔVDH) is compared withcomparison reference voltage (VM+VOS) on node N2 so that the pixel datacan be accurately compared and amplified while canceling the offset ofdifferential amplifier circuit 32.

The output signal of differential amplifier circuit 32 has a relativelylarge amplitude, and even when logical input thresholds of inverters 35and 36 vary due to variation in threshold voltage of TFTs, a voltagecorresponding to the read pixel data can be accurately produced on nodeN5 in accordance with the output signal of differential amplifiercircuit 32, and can be transferred to original data line DL (DLi orDLj).

The foregoing operations are sequentially repeated for each of the gatelines so that refreshing of the pixel data can be effected in a unit ofeach row of the display pixels.

FIG. 5 shows more specifically the structure of vertical scanningcircuit 2 shown in FIG. 1. In FIG. 5, vertical scanning circuit 2includes a vertical shift register 40 performing the shifting operationin accordance with a vertical scan start signal STV and a vertical scanclock signal VCK, to sequentially drives its outputs SR1–SRm to theselected state, and a buffer circuit 41 for producing data line drivesignals VG1–VGm in accordance with multi-selection inhibiting signalINHV and output signals SR1–SRm of vertical shift register 40.

Vertical scan start signal STV is made active when scanning of one frame(or one field) is completed in the display pixel matrix. Vertical shiftregister 40 has its select output initialized in accordance withactivation of vertical scan start signal STV, and resumes the shiftoperation starting at its initialized position in accordance withvertical scan clock signal VCK.

Buffer circuit 41 operates in accordance with multi-selection inhibitingsignal INHV to inhibit occurrence of simultaneous selection of two gatedrive signals among gate line drive signals VG1–VGm. Specifically, whenmulti-selection inhibiting signal INHV is at logically high level or atthe H level to be active, buffer circuit 41 sets all gate line drivesignals VG1–VGm to the unselected state regardless of the state ofoutput signals SR1–SRm of vertical shift register 40. Whenmulti-selection inhibiting signal INHV attains the logical low level orL level, buffer circuit 41 drives the gate line drive signals (verticalscan signals) to the select state in accordance with output signalsSR1–SRm of vertical shift register 40. Referring to FIG. 6, writing ofthe image data in the normal operation mode will now be describedbriefly.

In the normal operation mode, refresh mode instructing signal SELF is atthe L level. In this state, connection control signal S1 and a normaloperation mode instructing signal NORM are both active. Normal operationmode instructing signal NORM is an inverted signal of refresh modeinstructing signal SELF. In this case, vertical shift register 40performs the shift operation in accordance with vertical scan startsignal STV, multi-selection inhibiting signal INHV and vertical scanclock signal VCK, which in turn are applied from an external controller(not shown).

Specifically, vertical shift register 40 takes in vertical scan startsignal STV, performs the shift operation in accordance with asubsequently applied vertical scan clock signal VCK, and drives selectsignal SR1 for the first row to the selected state. When vertical scanstart signal STV rises, gate line drive signal VG1 is driven to theselected state in the next cycle. Thereafter, vertical shift register 40performs the shift operation in accordance with vertical scan clocksignal VCK, and sequentially drives gate line drive signals VG1–VGm.FIG. 6 shows, as an example, the sequence for successively selectinggate line drive signals VG1–VGm in accordance with the non-interlacesystem. Gate line drive signals VG1–VGm may be driven to the selectedstate in accordance with the interlace system. In the interlace system,a field formed of the gate lines on even-numbered rows and a field ofthe gate lines on odd-numbered rows are alternately selected.

While gate line drive signal VG1 is in the selected state, horizontalscanning circuit 3 shown in FIG. 1 performs the shift operation inaccordance with the horizontal clock signal (not shown), and an imagesignal corresponding to image data signal PD is transferred onto eachdata line. In this normal operation mode, all switch control signals S2,S3 and S4 are inactive, and even when differential amplifier circuit 32performs the differential amplification, the output of differentialamplifier circuit 32 in each of amplifier circuits AMPi and AMPj shownin FIG. 3 is isolated from corresponding data line so that the output ofthe differential amplifier does not exert an effect on the writing ofthe image data signal. All refresh circuits 5 may be kept inactive inthe normal operation mode.

FIG. 7 shows more specifically the operations of vertical shift register40 and buffer circuit 41 in the normal operation mode. As shown in FIG.7, vertical shift register 40 performs the shift operation in accordancewith vertical scan clock signal VCK. Therefore, output signals SR1 andSR2 of vertical shift register 40 are at logically higH level or at theH level during one clock cycle of vertical scan clock signal VCK.

In response to the rising of vertical scan clock signal VCK,multi-selection inhibiting signal INHV is at the H level for apredetermined period, and responsively, all output signals VG1–VGm ofbuffer circuit 41 are set at the L level. Therefore, whilemulti-selection inhibiting signal INHV is at the H level, all gate linedrive signals VG1–VGm are in the non-selected state.

When multi-selection inhibiting signal INHV falls to the L level, buffercircuit 41 drives gate line drive signals VG1–VGm in accordance withoutput signals SR1–SRm of vertical shift register 40. Even when outputsignals SR1 and SR2 of the vertical shift register 40 are both at Hlevel for a certain period when vertical shift register 40 performs theshift operation in response to rising of vertical scan clock signal VCK,multi-selection inhibiting signal INHV is at the H level, and therefore,multi-selection of gate line drive signals VG1 and VG2 applied frombuffer circuit 41 does not occur. As a result, the image data can bereliably written into the pixels on the selected row (gate line).

In accordance with horizontal scan signals H1, H2, . . . (see FIG. 2),the image data is successively written into the pixels connected to theselected row in accordance with a point sequential system. Instead ofthis point sequential system, however, such a writing system can beemployed that the image data signals are simultaneously written into thepixels on a selected row. In this system, write timing signals areapplied instead of horizontal scan signals H1, H2, . . . shown in FIG.2, and data line select gates 20 (generically representing 20 i and 20j) shown in FIG. 2 are simultaneously made conductive.

FIG. 8 is a timing chart illustrating an operation in refreshing ofvertical scanning circuit 2 shown in FIG. 5. FIG. 8 also illustratesswitch control signals S2–S4 and potential change on data line DL.

In the refresh mode, refresh mode instructing signal SELF is set to theH level, and connection control signal S1 is set to the L level. In thisstate, vertical shift register 40 performs the shift operation inaccordance with clock signal VCK. In response to the rising of verticalclock signal VCK, switch control signals S2 and S3 become the H levelfor a predetermined period. During this period of time, multi-selectioninhibiting signal INHV is at the H level, and gate line drive signal VG(generically representing VG1 and VG2) is in the inactive state.

After switch control signals S2 and S3 are driven to the inactive state,multi-selection inhibiting signal INHV attains the L level, andresponsively, gate line drive signal VG1 rises to the H level. Whilemulti-selection inhibiting signal INHV is at the H level, the operationof precharging data line DL is completed. When gate line drive signalVG1 is driven to the H level, the voltage on data line DL changes inaccordance with the voltage of the selected pixel element. Thecorresponding amplifier circuit amplifies this voltage change. Then,switch control signal S4 attains the H level, and the image dataamplified by the amplifier circuit is transmitted to the correspondingdata line DL.

When clock signal VCK rises to the H level again, switch control signalsS2 and S3 attain H level, gate line drive signal VG1 falls to the Llevel, and switch control signal S4 attains the L level. Thereby, dataline DL is precharged again. Thereafter, vertical scanning circuit 2performs the shift operation in accordance with vertical scan clocksignal VCK during the refresh mode, and sequentially drives the gatelines to the selected state.

By setting an H level period of multi-selection inhibiting signal INHVin the refresh mode to an appropriate time duration, gate line drivesignals VG1, VG2, . . . can be reliably driven to the selected stateafter corresponding data line DL is precharged to the predeterminedintermediate voltage level.

Vertical scan clock signal VCK for shifting the gate lines may beexternally applied both in the normal operation mode and in the refreshmode. The following description is made of a structure for internallyproducing vertical scan clock signal VCK in the refresh mode.

FIG. 9 schematically shows a structure of a refresh control circuit 6shown in FIG. 1. In FIG. 9, refresh control circuit 6 includes anoscillation circuit 55 performing an oscillation at a predeterminedcycle in response to activation of refresh mode instructing signal SELF,a buffer circuit 56 for buffering an output signal φVS0 of oscillationcircuit 55 to produce a refresh vertical scan clock signal VCKS, anone-shot pulse generating circuit 57 for producing a one-shot pulsesignal INHVS in response to rising of output signal φVS0 of oscillationcircuit 55, a counter 58 counting output signal φVS0 of oscillationcircuit 55, a one-shot pulse generating circuit 59 for generating aone-shot pulse signal φ2 when a count of counter 58 reaches apredetermined value, a one-shot pulse generating circuit 60 forproducing a one-shot pulse signal φ1 in response to activation ofrefresh mode instructing signal SELF, an OR circuit 61 receivingone-shot pulse signals φ1 and φ2 and producing a refresh vertical scanstart signal STVS, and an inverter circuit 62 for inverting a refreshmode instructing signal SELF to produce a normal operation modeinstructing signal NORM and a connection control signal S1.

Oscillation circuit 55 includes a ring oscillator 55 a performing anoscillating operation when refresh mode instructing signal SELF isactive, and an inverter 55 b for inverting and buffering the outputsignal of ring oscillator 55 a to produce the output signal φVS0. Ringoscillator 55 a includes a NAND circuit NG receiving refresh modeinstructing signal SELF on a first input, and an even number of stagesof cascaded inverters IV receiving the output signal of NAND circuit NG.Inverter IV in the final stage among these even number of stages ofinverters applies its output signal to a second input of NAND circuitNG.

Refresh control circuit 6 further includes a select circuit 70 aresponsive to normal operation mode instructing signal NORM and refreshmode instructing signal SELF, for selecting one of an externally appliedvertical scan clock signal VCKN and the refresh vertical scan clocksignal VCKS applied from buffer circuit 56 to produce vertical scanclock signal VCK, a select circuit 70 b responsive to normal operationmode instructing signal NORM and refresh mode instructing signal SELF,for selecting either one-shot pulse signal INHVS received from one-shotpulse generating circuit 57 or externally applied multi-selectioninhibiting signal INHVN to produce multi-selection inhibiting signalINHV, and a select circuit 70 c responsive to normal operation modeinstructing signal NORM and refresh mode instructing signal SELF, forselecting either an externally applied vertical scan start signal STVNor an output signal STVS of OR circuit 61 to produce vertical scan startsignal STV.

Select circuit 70 a includes an AND gate 70 aa receiving normaloperation mode instructing signal NORM and externally applied verticalscan clock signal VCKN, an AND gate 70 ab receiving refresh modeinstructing signal SELF and the output signal VCKS of buffer circuit 56,and an OR gate 70 ac receiving the output signals of AND gates 70 aa and70 ab to produce vertical scan clock signal VCK.

Select circuit 70 b includes an AND gate 70 ab receiving normaloperation mode instructing signal NORM and the externally appliedmulti-selection inhibiting signal INHVN, an AND gate 70 bb receivingrefresh mode instructing signal SELF and the pulse signal INHVSoutputted from one-shot pulse generating circuit 57, and an OR gate 70bc receiving the output signals of AND gates 70 ba and 70 bb to producemulti-selection inhibiting signal INHV.

Select circuit 70 c includes an AND gate 70 ca receiving normaloperation mode instructing signal NORM and externally applied scan startsignal STVN, an AND gate 70 cb receiving refresh mode instructing signalSELF and output signal STVS of OR circuit 61, and an OR gate 70 ccreceiving the output signals of AND gates 70 ca and 70 cb to producevertical scan start signal STV.

In the normal operation mode, refresh mode instructing signal SELF is atthe L level, and normal operation mode instructing signal NORM is at theH level. Therefore, select circuits 70 a, 70 b and 70 c output thevertical scan clock signal VCK, multi-selection inhibiting signal INHVand vertical scan start signal STV in accordance with the externallyapplied signals VCKN, INHVN and STVN, respectively. In the refresh mode,refresh mode instructing signal SELF is at the H level, and normaloperation mode instructing signal NORM is at the L level. Therefore,select circuits 70 a, 70 b and 70 c produce vertical scan clock signalVCK, multi-selection inhibiting signal INHV and vertical scan startsignal STV in accordance with the signals VCKS, INHVS and STVS appliedfrom buffer circuit 56, one-shot pulse generating circuit 57 and ORcircuit 61, respectively.

FIG. 10 is a timing chart illustrating an operation of a portionproducing the signals related to the refreshing in refresh controlcircuit 6 shown in FIG. 6. Referring to FIG. 10, the operation ofrefresh control circuit 6 shown in FIG. 9 will now be described.

When refresh mode instructing signal SELF is at the L level, oscillationcircuit 55 is inactive, and output signal φVS0 thereof is fixed at the Llevel. In refresh control circuit 6, therefore, the output signal VCKSof buffer circuit 56, one-shot pulse signal INHVS of one-shot pulsegenerating circuit 57 and pulse signal STVS of OR circuit 61 maintainthe L level.

Inverter 62 maintains normal operation mode instructing signal NORM atthe H level, and connection control signal S1 is also at the H level, sothat the image data signals are written into the pixels of the displaypixel matrix.

When only the holding of image data is to be performed, refresh modeinstructing signal SELF is driven to the H level. When refresh modeinstructing signal SELF attains the H level, NAND circuit NG in ringoscillator 55 a operates as an inverter, and ring oscillator 55 a startsthe oscillating operation. Thereby, the output signal φVS0 ofoscillation circuit 55 changes with the cycles determined by ringoscillator 55 a.

In response to the rising of refresh mode instructing signal SELF,one-shot pulse generating circuit 60 produces one-shot pulse signal φ1and accordingly, refresh vertical scan start signal STVS turns H-levelfor a predetermined period. When vertical scan start signal STVS attainsH level and refresh vertical scan clock signal VCKS applied from buffercircuit 56 then attains the H level, vertical scan start signal STVproduced in accordance with vertical scan start signal STV is set in thevertical shift register. In this state, initialization is merelyeffected on vertical shift register 40 shown in FIG. 5, and the outputsignals of the vertical shift register are all at the L level.

In accordance with refresh mode instructing signal SELF, select circuits70 a, 70 b and 70 c select output signal VCKS of buffer circuit 56,output signal INHVS of one-shot pulse generating circuit 57 and outputsignal STVS of OR circuit 61, and produces vertical scan clock signalVCK, multi-selection inhibiting signal INHV and vertical scan startsignal STV, respectively.

When refresh vertical scan clock signal VCKS applied from buffer circuit56 rises to the H level again, vertical shift register 40 shown in FIG.5 performs the shift operation to raise the output of its first stage tothe H level. One-shot pulse generating circuit 57 produces refreshmulti-selection inhibiting signal INHVS made H-level for a predeterminedperiod in response to the rising of output signal φVS0 of oscillationcircuit 55. When refresh multi-selection inhibiting signal INHVS attainsthe L level, vertical scan signal (gate line drive signal) VG1 producedfrom the vertical scanning circuit is driven to the H level.

Counter 58 performs the counting of output signal φVS0 of oscillationcircuit 55, and produces a count-up signal when it counts the rising ofthe signal φVS0 m times for the m gate lines of the display pixelmatrix. In response to the count-up signal of counter 58, one-shot pulsegenerating circuit 59 produces the pulse signal φ2 of one-shot, andresponsively, vertical scan start signal STVS rises to the H levelagain. When output signal φVS0 of oscillation circuit 55 rises to the Hlevel subsequently, vertical scan start signal STV produced based on thecurrent refresh vertical scan start signal STVS is set in the verticalshift register. In this state, the vertical shift register drivesvertical scan signal VGm for the last scanning line (gate line) in oneframe to the H level.

When output signal φVS0 of oscillation circuit 55 rises to the H levelagain, the vertical shift register raises gate line drive signal VG1 forthe first scanning line (gate line) to the H level again in accordancewith thus taken-in vertical scan start signal STV.

Therefore, counter 58 produces one-shot pulse signal φ2 each time itcounts output signal φVS0 of oscillation circuit 55 m times, andaccordingly refresh vertical scan start signal STVS can be producedafter completion of scanning of all the vertical scanning lines (gatelines) in the display pixel matrix.

The horizontal scanning is not required in the refreshing particularly.Therefore, refresh control circuit 6 does not produce the signalsrelated to the horizontal scanning. In this state, externally appliedsignals related to the horizontal scanning are all fixed at the L levelin logic, and the horizontal scanning circuit does not operate. Thisreduces power consumption.

In this refresh mode, one-shot pulse generating circuit 57 is used forproducing multi-selection inhibiting signal INHVS. Thus, the pulse widthof multi-selection inhibiting signal INHVS can be controlled such thatthe gate line is driven to the selected state after reliably prechargingdata line DL to predetermined voltage VM.

FIG. 11 schematically shows a structure of a portion for generatingswitch control signals S2–S4 in refresh control circuit 6. In FIG. 11,refresh control circuit 6 includes a one-shot pulse generating circuit75 for producing a one-shot pulse signal in response to rising of outputsignal φVS0 of oscillation circuit 55 shown in FIG. 9, a set/resetflip-flop 76 reset in response to the rising of output signal φVS0 ofoscillation circuit 55, to produce the switch control signal S4 from itsoutput Q, and an inverting delay circuit 77 for inverting and delayingby a predetermined time switch control signal S4. Set/reset flip-flop 76is set in response to the rising of the output signal of inverting delaycircuit 77, to set switch control signal S4 to the H level.

FIG. 12 is a timing chart illustrating an operation of refresh controlcircuit 6 shown in FIG. 11. Referring to FIG. 12, the operations ofrefresh control circuit 6 shown in FIG. 11 will now be described.

When oscillation signal φVS0 rises to the H level, one-shot pulsegenerating circuit 75 generates a one-shot pulse signal and accordinglyswitch control signals S2 and S3 attain the H level. The time width, forwhich switch control signals S2 and S3 are kept active, is made shorterthan the H level period of multi-selection inhibiting signal INHVS. Itis sufficient to ensure the time duration required for precharging thedata lines and setting of the offset in the amplifier circuits.

After switch control signals S2 and S3 are driven to the inactive state,multi-selection inhibiting signal INHVS is driven to the H level, andresponsively, gate line drive signal VGi is driven to the H level.

In response to the rising of oscillation signal φVS0, set/resetflip-flop 76 is reset, and switch control signal S4 from its output Qturns L-level to prohibit the transfer of the output signal of theamplifier circuit to the data line.

Switch control signal S4 maintains the inactive state for apredetermined period after gate line drive signal VGi is driven to theactive state. When a delay time of inverting delay circuit 77 elapses,the output signal of inverting delay circuit 77 rises to the H level sothat set/reset flip-flop 76 is set to drive switch control signal S4 tothe H level. At this time, gate line drive signal VGi is already at theH level, and accordingly the pixel data is already read onto the dataline and is amplified by the amplifier circuit. Thus, the data line canbe driven in accordance with the result of amplification to write thedata into the original pixel data.

A series of operations represented in FIG. 12 are repeated in responseto the rising of oscillation signal φVS0. By setting the delay time ofinverting delay circuit 77 to an appropriate time, after gate line drivesignal VGi is driven to the active state and then the amplifier circuitproduces amplified pixel data subsequently, amplified pixel data can beaccurately written into the original data.

In the case where vertical scan clock signal VCK, vertical scan startsignal STV and inhibiting signal INHV are externally applied in therefresh mode, it is not necessary to produce the control signals VCKS,INHVS and STVS related to the refresh as shown in FIG. 4. However, byinternally producing multi-selection inhibiting signal INHVS, the gateline drive signal can be accurately driven to the selected state aftercompletion of the data line precharging.

When the horizontal scan clock signal is externally applied even in therefresh mode, refresh mode instructing signal SELF is used to stop theshift operation of the horizontal scanning circuit. This can reduce thecurrent consumption in the refresh operation.

According to the first embodiment of the invention, as described above,each data line is provided with the amplifier circuit, in which the dataline is precharged to the predetermined voltage, and the output signalof the differential amplifier circuit is held in the capacitanceelement. Therefore, the offset due to variation in threshold voltage ofthe differential amplifier circuit is cancelled out, and the amplifyingoperation can be performed accurately.

In the refresh operation, since it is not necessary to change thedisplayed image, it is not required to change the voltage polarity ofpixel drive voltage Vcnt on the counter electrode. In this refreshoperation, however, liquid crystal display elements PX may be driven inan AC fashion. In this case, if pixel drive voltage Vcnt is changed inpolarity after completion of the refreshing of one frame, in thestructure shown in FIG. 2, the output signal of inverter buffer 35 isused for writing the inverted signal of the pixel data signal read fromthe pixel data into the original pixel. Alternatively, if counterelectrode drive voltage Vcnt is set to the intermediate voltage levelintermediate the voltages VH and VL corresponding to the H- and L-levels of the drive signal, the inverted pixel data signal outputtedfrom the amplifier circuit is merely written into the original pixel.

In addition, each data line may be provided with a switching element,which is placed between the refresh circuit and the display pixelmatrix, and is turned conductive in response to the refresh modeinstructing signal. In the normal operation mode, the refresh circuit isisolated from the corresponding data line, and thus the load on the dataline driver can be reduced.

[Second Embodiment]

FIG. 13 specifically shows a structure of differential amplifier circuit32 shown in FIG. 2. In FIG. 13, differential amplifier circuit 32includes a constant current section 32A supplying a constant current,and an amplifying section 32B for amplifying the signals on input nodesN1 and N2 to generate a resultant signal onto node N3. Constant currentsection 32A includes a resistance element RZ1 connected between a powersupply node ND1 and a node ND2, an N-channel thin film transistor (TFT)NQ1 connected between nodes ND2 and ND3 and having a gate connected tonode ND2, and an N-channel MOS transistor NQ2 forming a current mirrorcircuit with thin film transistor NQ1. Power supply node ND1 on a higherside receives a voltage V1, and power supply node ND3 on a lower sidereceives a voltage V2. The voltage levels of these voltages V1 and V2are merely required for precharge voltage VM to fall within the mostsensitive region of differential amplifier circuit 32. For example,voltages V1 and V2 correspond to voltages at the H- and L levels of theimage data signal, respectively. Typically, voltage V1 is set to thepower supply voltage level, but may be higher than the power supplyvoltage. Also, voltage V2 is typically set to the ground voltage, butmay be a negative voltage.

Amplifying section 32B includes a resistance element RZ2 connectedbetween power supply node ND1 and a node ND4, a resistance element RZ3connected between power supply node ND1 and a node ND5, an N-channelthin film transistor NQ3 connected between nodes ND4 and ND6 and havinga gate connected to node N2, an N-channel thin film transistor NQ4connected between nodes ND5 and ND6 and having a gate connected to nodeN1, a P-channel thin film transistor PQ1 connected between power supplynode ND1 and output node N3 and having a gate connected to node ND5, andan N-channel thin film transistor NQ0 connected between node N3 andpower supply node ND3 and having a gate connected to node NQ1. Nodes N1and N2 are non-inverted and inverted inputs of differential amplifiercircuit 32 shown in FIG. 2. Node N3 is an output node of differentialamplifier circuit 32 shown in FIG. 2.

Between nodes N3 and N2, a switching element 33 responsive to switchcontrol signal S3 is arranged. A capacitance element 34 is provided onnode N2. Resistance elements RZ1, RZ2 and RZ3 are formed of channelresistances or thin film resistances. Resistance elements RZ2 and RZ3have the same resistance value. Thin film transistors NQ3 and NQ4 areformed into the same geometry and size, and have the same transistorcharacteristics.

Description will now be given of the case where switching element 33 ismade conductive to electrically connect nodes N3 and N2.

Constant current section 32A causes a flow of current determined by theresistance of resistance element RZ1 and the channel resistance of thinfilm transistor NQ1. Thin film transistors NQ1 and NQ2 form a currentmirror circuit. If thin film transistors NQ1 and NQ2 are the same insize and geometry, thin film transistor NQ2 causes a current flow equalin magnitude to a current flowing through thin film transistor NQ1. Thinfilm transistor NQ2 functions as a constant current source transistor ina differential amplifier stage of amplifying section 32B. Thin filmtransistor NQ0 forms a current mirror circuit with thin film transistorNQ1, and drains out a current of a constant magnitude from output nodeN3.

When node N1 is higher in voltage level than node N2, thin filmtransistor NQ4 is larger in channel conductance than thin filmtransistor NQ3, and the voltage level of node ND5 lowers so that thechannel conductance of thin film transistor PQ1 increases to supply acurrent to output node N3. Since node N3 is connected to node N2 viaswitching element 33, the voltage level of node N2 rises.

When the voltage level of node N2 is higher than the voltage level ofnode N1, thin film transistor NQ3 is larger in channel conductance thanthin film transistor NQ4, and the voltage level of node ND5 is pulled upby resistance element RZ3 so that the channel conductance of thin filmtransistor PQ1 is reduced. In this case, thin film transistor NQ0discharges output node N3 to lower the voltage level of output node N3.Therefore, if an offset is not present in the threshold voltages of thinfilm transistors NQ3 and NQ4, the voltage levels of nodes N1 and N2 abecome equal to each other through negative feedback operation.

If offset VOS is present in threshold voltages of thin film transistorsNQ3 and NQ4, offset VOS affects the changes in channel conductance ofthin film transistors NQ3 and NQ4. If the threshold voltage of thin filmtransistor NQ4 is higher than that of thin film transistor NQ3, node N2is connected to a voltage level higher by offset VOS. Specifically,assuming that thin film transistors NQ3 and NQ4 are operated simply as asource-coupled logic, one of thin film transistors NQ3 and NQ4 turnsconductive, and the other turns non-conductive depending on the voltagelevels of nodes N1 and N2, and the output offset corresponding to offsetVOS of the threshold voltages thereof occurs on nodes N3 and N2.

Therefore, by rendering switching element 33 conductive to electricallycouple the output node and the inversion input node of differentialamplifier circuit 32, differential amplifier circuit 32 operates as avoltage follower, to enable storage of the voltage containing the offsetof differential amplifier circuit 32, in capacitance element 34.

In the amplifying operation of differential amplifier circuit 32,switching element 33 is made non-conductive. In this state, the voltagecontaining the offset information and held in capacitance element 34 iscompared with the signal applied to non-inversion node N1. Thereby, thechannel conductance of thin film transistor PQ1 is adjusted inaccordance with the result of comparison, and output node N3 is drivento the voltage level corresponding to the result of comparison.

Therefore, by using thin film transistors of the same size and the samecharacteristics in the differential stage, and by feeding back theoutput signal thereof in the precharge operation, the capacitanceelement can accurately holds the voltage having the offset of thedifferential amplifier circuit compensated for, and the pixel datasignal can be accurately amplified.

FIG. 14 shows another structure of differential amplifier circuit 32shown in FIG. 2. Differential amplifier circuit 32 shown in FIG. 14differs in configuration from differential amplifier circuit 32 in FIG.13 in the following point. In amplifying section 32B shown in FIG. 14, acurrent mirror stage for amplifying the result of differentiation isprovided for thin film transistors NQ3 and NQ4. This current mirrorstage includes a P-channel thin film transistor PQ2 connected betweenpower supply node ND1 and node ND4 and having a gate connected to nodeND4, and a P-channel thin film transistor PQ3 connected between powersupply node ND1 and node ND5 and having a gate connected to node ND4.The structure of differential amplifier circuit 32 shown in FIG. 14other than the above are the same as that of differential amplifiercircuit 32 shown in FIG. 13. The corresponding portions are allottedwith the same reference numerals, and description thereof will not berepeated.

Thin film transistors PQ2 and PQ3 have the same geometry and the samesize, and cause a current flow of the same magnitude therethrough.Therefore, change in voltage level of node ND4 is reflected on node ND5via MOS transistors PQ2 and PQ3 so that the amplification rate can belarger than in the use of resistance elements RZ2 and RZ3 shown in FIG.13.

Minute voltages read from the displaying pixel element can be detectedto drive accurately the inverter buffer in the next stage. Thus, theoutput signal of inverter buffer 36 shown in FIG. 2 can be set to thedefinite state at a faster timing, and it is possible to reduce the timerequired for refreshing the voltage held in the displaying pixelelement.

FIG. 15 shows still another structure of differential amplifier circuit32 shown in FIG. 2. Differential amplifier circuit 32 shown in FIG. 15differs in configuration from differential amplifier circuit 32 shown inFIG. 14 in the following points. In constant current section 32A, aP-channel thin film transistor PQ4 is connected between resistanceelement RZ1 and power supply node ND1, and an N-channel thin filmtransistor NQ5 arranged in parallel with N-channel thin film transistorNQ1 is connected between resistance element RZ1 and power supply nodeND3. Thin film transistors PQ4 and NQ4 receive on their gates an outputsignal of a NOR gate 80 receiving a test mode instructing signal TESTand refresh mode instructing signal SELF.

Test mode instructing signal TEST is set to the H level in the testoperation mode, which will be described later. Refresh mode instructingsignal SELF is set to the H level in the refresh mode. The structure ofdifferential amplifier circuit 32 shown in FIG. 15 other than the aboveare the same as that of differential amplifier circuit 32 shown in FIG.14. The corresponding portions are allotted with the same referencenumbers, and description thereof will not be repeated.

In the normal operation mode, in which the pixel data is rewritten, testmode instructing signal TEST and refresh mode instructing signal SELFare both at the L level, and the output signal of NOR circuit 80 is setto the H level. In this state, thin film transistor PQ4 isnon-conductive, and thin film transistor NQ5 is conductive so that nodeND2 is set to the voltage level of the lower side power supply voltageV2. Responsively, thin film transistors NQ1, NQ2 and NQ4 are renderednon-conductive to cut off a path of the operation current indifferential amplifier circuit 32.

In the refresh mode or test operation mode, refresh mode instructingsignal SELF or test mode instructing signal TEST is set to the H level.In this state, the output signal of NOR gate 80 is set to the L level sothat thin film transistor PQ4 is rendered conductive, and thin filmtransistor NQ5 is rendered non-conductive. Therefore, a path for currentflow is formed in constant current section 32A so that a constantcurrent flows through thin film transistors NQ2 and NQ4, and amplifyingsection 32 enters the operating state.

In differential amplifier circuit 32 shown in FIG. 15, the operationcurrent flows through the differential amplifier circuit only in thetest operation mode or the refresh operation mode. In the normaloperation mode, the path of the operation current of differentialamplifier circuit 32 is cut off so that the current consumption can bereduced in the normal operation mode.

In the structure of differential amplifier circuit 32 shown in FIG. 15,output node N3 is in the floating state in the normal operation mode.For preventing this floating state, a P-channel thin film transistorreceiving on its gate the output signal of NOR gate 80 may be connectedin parallel with output drive transistor PQ1.

According to the second embodiment of the invention, as described above,the differential amplifier circuit is formed of the constant currentsection and the amplifying section operating with the current suppliedfrom the constant current section being its operation current, and thisamplifying section is formed of the differential amplifying stage andthe transistors driving the output node in accordance with the outputsignal of the differential amplifying stage. Therefore, it is possibleto achieve the differential amplifier circuit that performs theamplifying operation with a simple structure and a reduced occupyingarea.

[Third Embodiment]

FIG. 16 shows a structure of a major portion of a display deviceaccording to a third embodiment of the invention. FIG. 16representatively shows displaying pixel element PX arrangedcorresponding to a crossing between gate line GL and data line DL.Similarly to the structure shown in FIG. 2, displaying pixel elements PXare arranged in rows and columns, data lines DL are arrangedcorresponding to the columns of display pixels, respectively, and gatelines GL are arranged corresponding to the rows of display pixels,respectively.

Amplifier circuit AMP is arranged corresponding to data line DL.Amplifier circuit AMP in FIG. 16 has the same structure as the amplifiercircuits AMPi and AMPj shown in FIG. 2.

Parasitic capacitance 27 is present on data line DL. Parasiticcapacitance 27 has capacitance value Cd.

Displaying pixel element PX includes an N-channel thin film transistor11 made conductive in response to the signal potential of gate line GL,to electrically couples a pixel electrode node (voltage holding node) 81to data line DL, a voltage holding capacitance element 82 connectedbetween pixel electrode node (voltage holding node) 81 and a boost node,an N-channel thin film transistor 83 transmitting pixel drive voltageVcom in accordance with the voltage held on pixel electrode node 81, anda liquid crystal display element 84 connected between a voltage appliedvia thin film transistor 83 and a counter electrode node. Counterelectrode node receives a counter electrode voltage Vcnt.

Voltage holding capacitance element 82 is formed of a channelcapacitance element utilizing a thin film transistor. When pixelelectrode node 81 holds the voltage at H level, a channel is formed, andcapacitance element 82 functions as a capacitance. When pixel electrodenode 81 holds a voltage at the L level, a channel is not formed, andvoltage holding capacitance element 82 functions as a capacitance havinga capacitance value of the parasitic capacitance. When a boost signal BSis supplied, voltage holding capacitance element 82 supplies asignificant amount of charges to pixel electrode node 81 through acharge pump operation to compensate for lowering of the voltage leveldue to a leakage current only when it holds the voltage at H level.

FIG. 17 is a signal waveform diagram illustrating an operation of thepixel in the refresh operation of the display device shown in FIG. 16.FIG. 17 illustrates operation waveforms in the case when pixel electrodenode 81 stores H-level data, and the voltage level lowers due to theleakage current. Referring to FIG. 17, description will now be given ofthe operation of refreshing the image data signal of the pixel shown inFIG. 16.

First, data line DL is precharged to the level of intermediate voltagelevel VM via a switching element included in amplifier circuit AMP.During this precharging operation period, boob signal BS at the level ofvoltage Vs is boosted to the level of voltage Vp. An amplitude Vbs ofboost signal BS is determined depending on the amount of chargessupplied to pixel electrode node 81 and the capacitance value ofcapacitance element 82. The voltage level of voltage Vs is alsodetermined appropriately depending on the level of the voltage held onpixel electrode node 81.

In accordance with boost signal BS, node 81 rises in voltage levelthrough the charge pump operation of capacitance element 82. Ifcapacitance element 82 has an ideal coupling coefficient equal to unity,the voltage on pixel electrode node 81 changes by voltage Vbs asillustrated in FIG. 17. This change amount of the voltage on pixelelectrode node 81 is determined by the amplitude of boost signal BS,capacitance Cs of capacitance element 82, the capacitance value of theparasitic capacitance of pixel electrode node 81 and the couplingcoefficient of the capacitance element 82.

After the precharge operation is completed, gate line GL is driven tothe selected state, to drive thin film transistor 81 into the conductivestate in order for performing the amplifying operation by amplifiercircuit AMP. In response to turn-on of thin film transistor 11, chargesaccumulated on node 81 are transmitted to corresponding data line DL. Inthis operation, boost signal BS maintains the level of boosted voltageVp. On data line DL, a voltage change corresponding to the voltage onpixel electrode node 81 occurs. Thus, a voltage change, which is a sumof a voltage change ΔVDH′ caused due to leakage and a voltage ΔVcorresponding to voltage Vbs caused by boost signal BS, occurs on dataline DL. If this voltage (ΔVDH′+ΔV) is substantially equal to voltageΔVDH, it is possible to compensate for lowering of the margin forH-level data in amplification by the differential amplifier in amplifiercircuit AMP, so that the amplifying operation can be performedaccurately.

Then, amplifier circuit AMP drives data line DL in accordance with theresult of amplification. In the amplifying operation by amplifiercircuit AMP, boost signal BS is restored to an original level of voltageVcom. When the voltage level of boost signal BS lowers, pixel electrodenode 81 is being driven by amplifier circuit AMP via data line DL sothat voltage lowering due to the capacitance coupling does not occur,and pixel electrode node 81 is maintained at the original voltage levelVH by amplifier circuit AMP.

When the operation of refreshing displaying pixel element PX iscompleted, gate line GL is driven to the unselected state, and data lineDL is driven to the level of intermediate voltage VM for refreshing theheld data in the next pixel row. Pixel electrode node 81 maintains therefreshed level of voltage VH.

The voltage on pixel electrode node 81 changes by a voltage level equalto the amplitude Vbs of boost signal BS if capacitance element 82 has acoupling coefficient equal to unity. Therefore, charges of Vbs·Cs areinjected into pixel electrode node 81 by the charge pump operation ofcapacitance element 82. In reading the pixel data, parasitic capacitance27 of data line DL and capacitance element 82 share the charges Vbs·Cs.Therefore, an incremental change ΔV of the voltage on data line DL canbe expressed by the following expression:ΔV=Vbs·Cs/(Cs+Cd)

By setting the amplitude of boost signal BS to an appropriate value, itis possible to compensate for voltage lowering of pixel electrode node81 due to the leakage current, and to compensate for lowering of readvoltage ΔVDH. Specifically, when the read voltage on data line DLassumes a voltage ΔVDH′ due to the voltage lowering of pixel electrodenode 81, the voltage level of data line DL is raised, through the chargepump operation by boost signal BS, by ΔV to be restored to the voltagelevel of read data ΔVDH, which is usually attained when no leakageoccurs.

In the arrangement of using boost signal BS, boost signal BS is driveneven when pixel electrode node 81 holds the L-level data. However,capacitance element 82 is formed of a channel capacitance element, andthe capacitance value thereof contains only the capacitance value ofparasitic capacitance when L-level image signal is stored. Even when thecharge pump operation is performed in accordance with boost signal BS,the amount of injected charges is very small, and it is possible tosuppress sufficiently the rising of voltage level of pixel electrodenode 81.

FIG. 18 schematically shows a sectional structure of voltage holdingcapacitance element 82 shown in FIG. 16. In FIG. 18, voltage holdingcapacitance element 82 has a structure similar to that of an N-channelthin film transistor, and is formed on a glass substrate 91. Capacitanceelement 82 includes an N-type polycrystalline silicon film 92 formed onglass substrate 91, an intrinsic polycrystalline silicon film 93 formedadjacently to N-type polycrystalline silicon film 92 on the surface ofglass substrate 91, a gate insulating film 94 formed on intrinsicpolycrystalline silicon film 93, a gate electrode 95 formed on gateinsulating film 94 facing to intrinsic polycrystalline silicon film 93,an electrode 97 electrically connected to gate electrode 95, and anelectrode 99 electrically connected to N-type polycrystalline siliconfilm 92.

Gate insulating film 94 is made of, e.g., silicon dioxide, and gateelectrode 95 is made of, e.g., chrome. Electrodes 97 and 99 are made of,e.g., aluminum.

N-type polycrystalline silicon film 92 is electrically connected tointrinsic polycrystalline silicon film 93 when a channel is formed.

Electrode 97 is connected to pixel electrode node 81, and electrode 99receives boost signal BS.

Capacitance element 82 has an overlap portion 98 formed between gateelectrode 95 and intrinsic polycrystalline silicon film 93. Acapacitance of a structure formed of gate electrode 95, intrinsicpolycrystalline silicon film 93 and N-type polycrystalline silicon film94 shown in FIG. 18, is a so-called “channel capacitance”. On the basisof the voltage on electrode 99, a voltage larger than the thresholdvoltage of the N-channel thin film transistor is applied betweenelectrode 97 corresponding to the gate electrode and electrode 99corresponding to the source electrode. Responsively, an N-channel layeris formed in overlap portion 98 at the surface of intrinsicpolycrystalline silicon film 93 beneath gate electrode 95, and anelectrostatic capacitance is formed, with gate electrode 95 on thechannel formed in overlap portion 98 being one electrode, and also withthe channel layer electrically connected to N-type polycrystallinesilicon film 92 being the other electrode. When pixel electrode node 81holds the H-level data, the channel is formed in overlap portion 98, andcapacitance element 82 functions as a capacitance of capacitance valueCs.

When pixel electrode node 81 holds L-level data, a voltage betweenelectrodes 97 and 99 is smaller than the threshold voltage of the N-typethin film transistor, and the channel capacitance is not formed. In thisstate, capacitance element 82 has only a minute parasitic capacitancepresent in overlap portion 98, as its capacitance component. In thiscase, therefore, even if the voltage level of boost signal BS applied toelectrode 99 rises, the charge pump operation is performed through theparasitic capacitance existing in overlap portion 98, and only a verysmall amount of charges are injected into pixel electrode node 81.Therefore, rising of the voltage on pixel electrode node 81 can besubstantially suppressed while the L-data data is held.

Thereby, it is possible to read the pixel data accurately onto data lineDL while compensating for lowering of the voltage level of the H-leveldata, and the level of voltage Vs corresponding to the L level of boostsignal BS need only be appropriately determined in accordance withvoltage level VH of the H-level data held on pixel electrode node 81,and may be the ground voltage or common electrode voltage Vcom. It ismerely required to determine the voltage level of the boost signal BS atthe L level such that a channel capacitance is formed in capacitanceelement 82 when pixel electrode node 81 stores H-level data, and thechannel layer is not formed in the channel capacitance element in thecase of storage of the L-level data.

FIG. 19 schematically shows a structure of a portion for generatingboost signal BS shown in FIG. 16. In FIG. 19, a boost signal generatingportion is formed of a one-shot pulse generating circuit 100 generatinga one-shot pulse signal in response to the rising of refreshmulti-selection inhibiting signal INHVS applied from one-shot pulsegenerating circuit 57. One-shot pulse generating circuit 100 receivesthe voltages Vp and Vs as operation power supply voltages. The one-shotpulse signal outputted from one-shot pulse generating circuit 100 isused as boost signal BS.

FIG. 20 is a timing chart illustrating an operation of one-shot pulsegenerating circuit 100 shown in FIG. 19. Referring to FIG. 20, anoperation of one-shot pulse generating circuit 100 shown in FIG. 19 willnow be described briefly.

As shown in FIG. 9 previously, refresh multi-selection inhibiting signalINHVS is made H-level for a predetermined period in synchronization withthe rising of vertical scan clock signal VCKS (VCK). More strictly,refresh multi-selection inhibiting signal INHVS is produced inaccordance with output signal φVS0 of oscillation circuit 55 as shown inFIG. 9. In response to the rising of refresh multi-selection inhibitingsignal INHVS, one-shot pulse generating circuit 100 produces a pulsesignal of one shot, and responsively, poop signal BS rises to the Hlevel. When boost signal BS rises to the H level, gate line GL is stillin an unselected state as illustrated in FIG. 20, and the prechargeoperation is effected on the data line.

When refresh multi-selection inhibiting signal INHVS falls to the Llevel, a selected gate line GL (GLa) is driven to the H level. Afterselected gate line GLa rises to the H level and the output signal of thecorresponding amplifier circuit is transmitted to the pixel electrodenode, boost signal BS falls to the L level. Therefore, boost signal BScan be driven to the L level at a given point in a period, for which theselected gate line GL is at the H level.

When the operation of refreshing selected gate line GL (GLa) iscompleted, the refresh operation for the next row (gate line) isexecuted in response to vertical scan clock signal VCKS. In this case,next gate line GLb attains the H level after refresh multi-selectioninhibiting signal INHVS falls to the H level. For gate line GLb,therefore, boost signal BS is made H-level for a predetermined period.

Boost signal BS may be commonly applied to the respective pixels of thedisplay pixel matrix. In an unselected pixel, the voltage holdingcapacitance element performs the charge pump operation when thecorresponding gate line is not selected. In this case, charges areinjected into the pixel electrode node (voltage holding node), and arethen extracted out in response to the falling of boost signal BS. In thedisplaying pixel element connected to the unselected gate line,therefore, the voltage level of the voltage holding node (pixelelectrode node) does not change when one refresh operation cycle iscompleted.

The voltage level of boost signal BS may be controlled in units of pixelrows. Based on the output signal of the vertical shift register in thevertical scanning circuit (see FIG. 5), boost signal BS is transmittedonly to a selected gate line. According to such configuration, thedriving load of boost signal BS can be reduced to reduce the powerconsumption.

According to the third embodiment of the invention, as described above,the channel capacitance is used as the voltage holding capacitanceelement in the displaying pixel element, and the charge pump operationis performed when the voltage holding node holds the H-level signal.Therefore, even when the voltage level of the H-level data lowers due toa leakage current, such lowering can be reliably compensate for. In therefresh mode, a sufficient read voltage can be read onto the data line,and the amplifying operation can be performed accurately for rewritingthe pixel data.

[Fourth Embodiment]

FIG. 21 schematically shows a structure of a main portion of a displaydevice according to a fourth embodiment of the invention.

Referring to FIG. 21, display pixel matrix 1 includes displaying pixelelements PX arranged in rows and columns. FIG. 21 representatively showsdisplaying pixel elements PX arranged in one row. Data lines DL1, DL2, .. . DLn are arranged corresponding to the respective columns ofdisplaying pixel elements PX.

Data lines DL1–DLn are provided at middle portions thereof withswitching gates SW1, SW2, . . . and SWn. These switching gates SW1–SWnare commonly supplied with an output signal of a NOR circuit 106receiving refresh mode instructing signal SELF and test mode instructingsignal TEST. In the refresh mode and the test mode, therefore, switchinggates SW1–SWn are made non-conductive to bi-divide corresponding datalines DL1, DL2, . . . and DLn.

Refresh circuits 5 t and 5 b are arranged on the opposite sides, in thecolumn direction, of display pixel matrix 1. Refresh circuits 5 t and 5b each include amplifier circuits (see FIG. 2) provided corresponding todata lines DL1–DLn. Test circuits 102 t and 102 b are arrangedadjacently to refresh circuits 5 t and 5 b, for reading data amplifiedby the amplifier circuits in refresh circuits 5 t and 5 b. Test circuits102 t and 102 b are commonly coupled to output circuit 104. When testmode instructing signal TEST is active, output circuit 104 externallyoutputs the data received from test circuits 102 t and 102 b.

As shown in FIG. 22, switching gate SW bi-divides data line DL intodivided data lines DDLt and DDLb in the refresh mode and the testoperation mode. Divided data line DDLt is coupled to amplifier circuitAMPt included in refresh circuit 5 t, and divided data line DDLb iscoupled to amplifier circuit AMPb included in refresh circuit 5 b.Assuming that each of data lines DL1–DLn has the parasitic capacitanceof the capacitance value of Cd, each of divided data lines DDLt and DDLbhas a parasitic capacitance of Cd/2. In the case where the voltageholding capacitance included in displaying pixel element PX has thecapacitance value of Cs, therefore, voltages ΔVDH and ΔVDL placed ondivided data lines DDLt and DDLb are expressed by the followingequations, respectively:ΔVDH=(VH−VL)·Cs/2·(Cs+Cd/2),ΔVDL=(−VH+3·VL)·Cs/2·(Cs+Cd/2)

The capacitance value of the data line is decreased from Cd to Cd/2, andread voltages ΔVDH and ΔVDL appearing on divided data lines DDLt andDDLb can be increased nearly to doubled values. Thereby, even when thevoltage held by the displaying pixel element is low, amplifier circuitsAMPt and AMPb can accurately perform the amplifying operation forrefreshing the display pixel data and for external reading out.

FIG. 23 schematically shows structures of refresh circuit 5 t and testcircuit 102 t shown in FIG. 21. In FIG. 23, divided data lines DDLti,DDLtj and DDLtk are respectively coupled to gate line drivers 22 i, 22 jand 22 k via isolation gates 24 i, 24 j and 24 k selectively madeconductive in response to connection control signal S1. These gate linedrivers 22 i, 22 j and 22 k as well as isolation gates 24 i, 24 j and 24k have the same structures as those shown in FIG. 2.

Refresh circuit 5 t includes amplifier circuits AMPti, AMPtj and AMPtkprovided corresponding to divided data lines DDLti, DDLtj and DDLtk,respectively. Amplifier circuits AMPti, AMPtj and AMPtk have the samestructure as the amplifier circuit AMPi shown in FIG. 2.

Test circuit 102 t includes test select gates TSGti, TSGtj and TSGtkprovided corresponding to amplifier circuits AMPti, AMPtj and AMPtk,respectively. In the test operation, test select gates TSGti, TSGtj andTSGtk are made conductive in response to test horizontal scan signalsTHi, THj and THk made sequentially active, to transmit the outputsignals of corresponding amplifier circuits AMPti, AMPtj and AMPtk to acommon test data line 110, respectively. This test common data line 110is coupled to output circuit 104 shown in FIG. 21. The common test dataline 110 may be provided with a main amplifier, through which the testdata is transferred to output circuit 104.

Refresh circuit 5 b and test circuit 102 b shown in FIG. 21 have thestructures similar to those of refresh circuit 5 t and test circuit 102t shown in FIG. 23. Therefore, refresh circuits 5 t and 5 b can haveindividually the amplifier circuits activated for refreshing the pixeldata. Refresh circuits 5 t and 5 b may be concurrently activated foramplifying the image data signals, and may alternatively be activated toperform the amplification in accordance with the position of a selectedgate line.

FIG. 24 shows more specifically the structures of refresh circuits 5 tand 5 b as well as test circuits 102 t and 102 b shown in FIG. 21. Theserefresh circuits t5 and 5 b have the same structure, and test circuits102 t and 102 b also have the same structure. Therefore, FIG. 24representatively shows amplifier circuit AMP and a test select gate TSGin the refresh circuit provided for one divided data lines DDL.

Similarly to the structure shown in FIG. 2, amplifier circuit AMP hasswitching gates 30, 33 and 37, capacitance element 34, differentialamplifier circuit 32 differentially amplifying a charged voltage ofcapacitance element 34 and a signal on divided data line DDL, and twostages of cascaded inverter buffers 35 and 36 for producing a signal ofa large drive power by amplifying the output signal of differentialamplifier circuit 32.

In the test circuit, test select gate TSG transfers the output signal ofinverter buffer 36 to common test data line 110. Test select gate TSGreceives a test horizontal scan signal TH.

As shown in FIG. 24, amplifier circuit AMP amplifies a minuteaccumulated voltage of the displaying pixel element, and transfers aresultant signal via read data line 110 to output circuit 104 shown inFIG. 21. Thereby, binary data can be read out externally throughamplification of the minute pixel voltage. In the outside, an arraytester for detecting a minute signal is not required, but an inexpensiveLSI tester can be used. In accordance with test horizontal scan signalTH, the pixel data for one row can be sequentially and successively readout to determine the logical levels of the binary pixel data. Thus, itis not necessary to determine the logical level of the minute voltagelevel, and the test time can be reduced.

Test select gate TSG may be formed of a tristate buffer, or of a CMOStransmission gate.

For the structure for producing switch control signals S2–S4 andconnection control signal S1 in the test mode, the structure shown inFIG. 11 can be used. Output signal φVS0 of the oscillation circuit isproduced when test mode instructing signal TEST is active. For othercontrol signals, the configuration similar to that shown in FIG. 9 canbe utilized. Amplifier circuit AMP can perform the accurate amplifyingoperation while canceling the offset even in the test mode, and thestored pixel data in a pixel element can be read externally.

FIG. 25 schematically shows a structure of a portion for producingsignals related to the gate line selection of the display deviceaccording to the fourth embodiment of the invention. The structure ofthe control signal generating portion shown in FIG. 25 differs in thestructure from the control signal generating portion shown in FIG. 9 inthe following points. Oscillation circuit 55 receives, instead ofrefresh mode instructing signal SELF, an output signal of an OR circuit120 receiving refresh mode instructing signal SELF and test modeinstructing signal TEST. The output signal of OR circuit 120 is alsoapplied to one-shot pulse generating circuit 60 and inverter 62.

Select circuits 70 a–70 c are supplied with an output signal of an ORcircuit 122 receiving refresh mode instructing signal SELF and test modeinstructing signal TEST, instead of the refresh mode instructing signal.

For accommodating with the bi-divided structure of the display pixelmatrix, there is provided a counter 124 that has a count reset inaccordance with refresh vertical scan start signal STVS, and countsoutput signal φVS0 of oscillation circuit 55. In accordance with thecount value, counter 124 generates an activating signal ENT activatingrefresh circuit 5 t and test circuit 102 t, and an activating signal ENBactivating refresh circuit 5 b and test circuit 102 b.

The other structure of the control signal generating portion shown inFIG. 25 is the same as that of the control signal generating portionshown in FIG. 9. The corresponding portions are allotted with the samereference numbers, and description thereof will not be repeated.

FIG. 26 is a timing chart illustrating an operation of counter 124 inthe control signal generating portion shown in FIG. 25. An operation ofcounter 124 will now be described with reference to FIG. 26.

In the test mode, test mode instructing signal TEST is at the H level,and accordingly the normal operation mode instructing signal NORM is atthe L level. In accordance with output signal φVS0 of oscillationcircuit 55, buffer circuit 56 outputs a refresh vertical scan clocksignal VCKF at predetermined cycles. When refresh vertical scan startsignal STVS outputted from OR circuit 61 is made active, counter 124sets its count to the initial value, and activates the activating signalENT. Thereby, a test is performed of the divided data lines (DDLt) in anupper region of display pixel matrix 1 shown in FIG. 21. Thus, the gateline drive signals starting from signal VG1 are sequentially driven tothe selected state, and the amplification and reading of the pixel dataare sequentially executed.

After all the gate lines crossing divided data line DDLt are driven inthe display pixel matrix, the gate lines crossing divided data line DDLbare sequentially selected. For selecting first gate line VGi, counter124 sets activating signal ENT and ENB to L- and H-levels in accordancewith its count value, respectively. Activating signals ENT and ENB areactivated in synchronization with output signal φVS0 of oscillationcircuit 55.

Thereby, refresh circuit 5 b and test circuit 102 b shown in FIG. 21 areactivated, and a test is performed on the pixels connected to the gatelines crossing divided data lines DDLb in the lower region.

By counting the number of the selected data lines, associated refreshcircuit and test circuit can be activated in accordance with theposition of the selected gate line even in the bi-divided display pixelmatrix structure. In bi-divided display pixel matrix structure, the gatelines may be selected in accordance with the interlace system. Even inthis case, through setting of a count-up value of counter 124 to anappropriate value (half the number of gate lines in one field), therefresh circuit and the test circuit in the upper region as well as therefresh circuit and the test circuit in the lower region can beaccurately and selectively activated in accordance with the position ofa selected gate line.

Such a configuration may be employed, in which in the test mode, thepixel data are read in parallel onto divided data lines DDLt and DDLb ofthe display pixel matrix, and both refresh circuits 5 t and 5 b shown inFIG. 21 perform the amplifying operation. In the test mode, verticalscan start signal STVS is set to the head position in each dividedregion of vertical shift register 40 shown in FIG. 5. Thereby, the gatelines in the respective divided regions can be simultaneously selectedfor the divided data lines DDLt and DDLb to amplify and read the displaypixel data. This parallel amplifying operation of the display pixel datamay be executed in the refresh mode.

FIG. 27 schematically shows a structure of a portion for generating testhorizontal scanning signals TH (THi and others) shown in FIG. 23. InFIG. 27, the test horizontal scan signal generating section includes anoscillation circuit 130 that is activated in response to activation oftest mode instructing signal TEST, to perform the oscillating operationat a predetermined cycle to provide the oscillating signal as a testhorizontal clock signal HCKS, an AND gate 132 receiving oscillationsignal HCKS and switch control signal S4 shown in FIG. 2, an AND gate134 receiving the output signal of AND gate 132 and activating signal EN(ENT or ENB) received from counter 124 shown in FIG. 25, and a shiftregister 136 performing the shift operation in accordance with theoutput signal of AND gate 134 to produce test horizontal scanningsignals TH1–THn. The shift register 136 is reset in response to theactivation of vertical scan clock signal VCKS. Shift register 136 may bereset in response to vertical scan start signal STV.

The test horizontal scan signal generating portion shown in FIG. 27 isprovided for each of test circuits 102 t and 102 b shown in FIG. 21.Therefore, activating signal EN is the activating signal ENT when thetest select signal generating section shown in FIG. 27 is provided fortest circuit 102 t, and is activating signal ENB when the test selectsignal generating section in FIG. 27 is provided for test circuit 102 b.

FIG. 28 is a timing chart illustrating an operation of the test selectsignal generating section shown in FIG. 27. Referring to the timingchart shown in FIG. 28, description will now be given on the operationof the circuitry shown in FIG. 27.

In the normal operation mode and the refresh mode, a test modeinstructing signal TST is inactive, and oscillation signal HCKSgenerated from oscillation circuit 130 is fixed at the L level. In thiscase, therefore, even when activating signal EN is made active in therefresh mode, AND gate 134 generates the output signal at the L level,and shift register 136 does not perform the shift operation.

In the test operation mode, test mode instructing signal TEST is madeactive, and oscillation circuit 130 performs the oscillating operationat a predetermined cycle. When vertical scan clock signal VCKS is madeactive and one of the gate lines is driven to the selected state, switchcontrol signal S4 is driven to the active state after the amplifyingoperation of the amplifier circuit in the refresh circuit. In responseto the activation of switch control signal S4, AND gate 132 passesoscillation signal HCKS applied from oscillator circuit 130therethrough.

Shift register 136 is reset to select the head position in response tothe activation of vertical scan clock signal VCKS. Therefore, shiftregister 136 drives first test horizontal scan signal TH1 to the activestate in response to the activation of switch control signal S4.Thereafter, shift register 136 performs the shift operation inaccordance with oscillation signal HCKS of oscillation circuit 130 todrive sequentially test horizontal scan signals TH1–THn starting at thesignal TH1 to the selected state.

After shift register 136 drives the last test select signal THn to theselected state, it maintains all test select signals TH1–THn in theinactive state. When vertical scan clock signal VCKS is activated forthe driving of the next gate line, shift register 136 is reset again,and the shift operation for the test select signals starting from testselect signal TH1 is executed.

If shift register 136 is provided commonly to test circuits 102 t and102 b, a combined signal (logical AND signal) of each of test horizontalscan signals TH1–THn applied from shift register 136 and activatingsignal EN (ENT or ENB) is used for the test horizontal scan signals.

If the horizontal scan register used in the normal operation mode isutilized as shift register 136, the horizontal shift register issimilarly activated to perform the shift operation in accordance withtest mode instructing signal TEST and switching control signal S4. Byusing activating signals ENT and ENB, test horizontal scan signals fortest circuits 102 t and 102 b are generated.

In the structure shown in FIG. 21, the display pixel matrix isbi-divided by switching elements SW1–SWn. However, even when the refreshcircuit and the test circuit are arranged on one side of the displaypixel matrix, the test of the displaying pixel elements can likewise beperformed by using the refresh circuit. In the structures shown in FIGS.25 and 27, it is merely required to produce the test control signals forone test circuit.

According to the fourth embodiment of the invention, as described above,the display pixel matrix has the bi-divided structure, and the refreshcircuits are provided for the divided data lines so that the parasiticcapacitances of the divided data lines can be reduced, and largevoltages can be read from the displaying pixel elements. Therefore, thedata of displaying pixel elements can be accurately amplified andrewritten.

By using the result of amplification of the refresh circuit, the testcircuit reads out externally the amplified data of the displaying pixelelements. It is not necessary to detect a minute signal by a tester, andthe display pixel data of a large amplitude can be read out externallyso that the test can be performed fast with an inexpensive tester.

[Fifth Embodiment]

FIG. 29 schematically shows another structure of displaying pixelelement PX. Displaying pixel element PX shown in FIG. 29 includes anN-channel thin film transistor 83 transmitting a common pixel drivevoltage to liquid crystal display element 84 in accordance with the heldvoltage of capacitance element 12. The other electrode of the liquidcrystal display element is a counter electrode. N-channel thin filmtransistor 11 couples capacitance element 12 to data line DL inaccordance with the signal potential of gate line GL.

Even if liquid crystal display element 80 is driven by thin filmtransistor 83 as shown in FIG. 29, the refreshing and reading forexternal output of the held voltage of capacitance element 12 can beaccurately performed similarly.

FIG. 30 shows still another structure of displaying pixel element PX. Indisplaying pixel element PX shown in FIG. 30, liquid crystal displayelement 13 is driven in accordance with the held voltage of capacitanceelement 82 formed of a channel capacitance. Boost signal BS applied tocapacitance element 82 can compensate for the voltage lowering of the Hlevel data held on the pixel electrode node due to the leakage currentso that the read voltage read onto data line DL can be made sufficientlylarge. Therefore, even in the case where gate line GL is selected, andthin film transistor 11 is made conductive to read the held voltage ofcapacitance element 82 onto data line DL for refreshing, the heldvoltage can be accurately refreshed. Also, in the operation of readingthe held voltage of capacitance element 82 for external output, the heldvoltage can be accurately amplified by the amplifier circuit to beoutputted externally.

FIG. 31 shows yet another structure of displaying pixel element PX.Displaying pixel element PX shown in FIG. 31 includes anelectroluminescent light emitting element 142. Electroluminescent lightemitting element 142 is driven by a P-channel thin film transistor 140,which in turn is selectively rendered conductive in accordance with theheld voltage of capacitance element 12. When thin film transistor 140 ismade conductive, electroluminescent light emitting element 142 receivesa high-level power supply voltage Vh on its anode electrode.Electroluminescent light emitting element 142 receives low-level powersupply voltage V1 on its cathode electrode. These voltages Vh and V1 maybe the power supply voltage and the ground voltage, respectively.

Capacitance element 12 is coupled to data line DL via N-channel thinfilm transistor 11 responsive to the signal potential of gate line GL.In the structure of displaying pixel element PX shown in FIG. 31,conduction and non-conduction of thin film transistor 140 are determinedin accordance with the held voltage of capacitance element 12. By usingthe refresh circuit already described, it is therefore possible tocompensate accurately for the lowering of the held voltage ofcapacitance element 12 due to the leakage current, to restore the heldvoltage to the original voltage level. By using the test circuit, it ispossible to detect a failure in displaying pixel element PX.

In the structure of displaying pixel element PX shown in FIG. 31, thechannel capacitance 82 shown in FIG. 30 may be employed as thecapacitance element.

Accordingly, the invention can be applied to various kinds of displayingpixel elements, provided that a capacitance element is utilized for anelement holding the pixel data signal voltage, and the held voltagedetermines the display state of the display pixel.

[Sixth Embodiment]

FIG. 32 schematically shows a structure of a main portion of a displaydevice according to the sixth embodiment of the invention. In thestructure shown in FIG. 32, data line DL is provided with an isolationgate 150. Amplifier circuit AMP is coupled to data line DL via isolationgate 150. Isolation gate 150 is selectively made conductive inaccordance with the output signal of an OR circuit 152 receiving refreshmode instructing signal SELF and test mode instructing signal TEST. Theoutput signal of amplifier circuit AMP is selected by test select gateTSG in the test mode, and is transferred to an output circuit (notshown).

In the normal operation mode other than the refresh mode and the testmode, isolation gate 150 maintains the non-conductive state to isolatedata line DL from amplifier circuit AMP. In the test mode or the refreshmode, isolation gate 150 is made conductive to couple data line DL toamplifier circuit AMP. Therefore, it is possible to reduce the load ondata line DL in the normal operation mode, and the data line driver canrapidly drive data line DL in accordance with the write image datasignal.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

INDUSTRIAL APPLICABILITY

This invention can be generally applied to a circuit for driving adisplay panel of a display device.

Devices, which utilizes the liquid crystal panel, include displaydevices of stand-alone personal computers and display devices ofportable devices. Such portable devices include laptop computers,portable phones, PDAs (Personal digital Assistants) and game equipments.

According to the invention, as described above, the data line isprecharged to a predetermined potential, and the differential amplifiercircuit is configured to operate as a voltage follower to set thecomparison reference voltage level. Therefore, even when variation inthreshold voltage of the differential amplifier circuit causes theoffset, the image information read from a displaying pixel element canbe accurately amplified. Thus, refreshing of the accumulated voltage ofthe displaying pixel element and reading of the accumulated voltage ofthe displaying pixel element for external output can be performed.

1. An image display device comprising: a plurality of displaying pixelelements arranged in rows and columns; a plurality of gate lines,arranged corresponding to the respective display pixel rows, eachconnected to the displaying pixel elements on a corresponding row, forselecting the display pixels on the corresponding row when said each isselected; a plurality of data lines, arranged corresponding to therespective display pixel columns, each connected to the displaying pixelelements in a corresponding column, for transferring pixel data to thedisplaying pixel elements in the corresponding column; a peripheralcontrol circuit responsive to an operation mode instructing signal fordriving a selected gate line of said plurality of gate lines to aselected state to supply an accumulated charge of a correspondingdisplay pixel onto a corresponding data line; and a plurality ofamplifier circuits, arranged corresponding to the respective pixelcolumns, each for amplifying a voltage applied onto the data line in acorresponding column when activated, each amplifier circuit including acapacitance element, a differential amplifier circuit having a firstinput coupled to a corresponding data line and a second input connectedto said capacitance element for differentially amplifying signals on thefirst and second input signals when made active, a first switchingelement coupling said first input to a reference power supply supplyinga predetermined voltage in response to a first switch control signal,and a second switching element coupling an output of said differentialamplifier circuit to said capacitance element in response to a secondswitch control signal.
 2. The image display device according to claim 1,wherein said peripheral control circuit responsive to said operationmode instructing signal for producing the first and second switchcontrol signals to render the first and second switching elementsconductive for a predetermined period, and then producing a selecttiming control signal for driving a selected gate line among saidplurality of gate lines to a selected state.
 3. The image display deviceaccording to claim 1, wherein each of said plurality of amplifiercircuits further includes a data line drive circuit for transmitting anoutput signal of said each amplifier circuit to a corresponding dataline after the selected gate line is driven to the selected state, andsaid data line drive circuit stops transference to the correspondingdata line of the output signal of said differential amplifier circuitwhen the first and second switching elements are made conductive.
 4. Theimage display device according to claim 1, wherein said first input is anon-inversion input, and said second input is an inversion input.
 5. Theimage display device according to claim 1, wherein said differentialamplifier circuit includes: first and second field effect transistorshaving gates respectively connected to the first and second inputs; aconstant current circuit coupled to said first and second field effecttransistors, for causing an operation current of a constant magnitude toflow through said first and second field effect transistors; loadelements arranged corresponding to said first and second field effecttransistors, respectively; an output transistor having a gate coupled toa conduction node of the first field effect transistor for producing theoutput signal of said differential amplifier circuit; and a constantcurrent supply transistor coupled to the output node of saiddifferential amplifier circuit, for causing a flow of a currentcorresponding to the current supplied by said constant current circuitthrough said output node.
 6. The image display device according to claim1, wherein said differential amplifier circuit includes: a differentialstage formed of a pair of first and second field effect transistorshaving respective gates connected to the first and second inputs; acurrent mirror stage coupled to said first and second field effecttransistors; an output transistor having a gate coupled to a conductionnode of the first field effect transistor for producing the outputsignal of said differential amplifier circuit; a constant currentcircuit for producing a constant current determining an operationcurrent of said differential stage; and a current supply transistorcoupled to said output transistor for producing a current correspondingto the current supplied by said constant current circuit on the outputnode of said differential amplifier circuit.
 7. The image display deviceaccording to claim 1, wherein the predetermined voltage supplied by saidreference power supply is at a voltage level intermediate between a highlevel and a low level of a signal transmitted to the data lines.
 8. Theimage display device according to claim 1, further comprising: a circuitfor maintaining the amplifier circuits inactive in a normal operationmode.
 9. The image display device according to claim 1, furthercomprising: a plurality of third switching elements arranged for thedata lines, respectively, and made selectively non-conductive to dividecorresponding data lines in a specific operation mode including arefresh mode of operation other than a normal operation mode, whereinthe amplifier circuits are arranged corresponding to divided data lines,respectively.
 10. The image display device according to claim 1, whereineach of the displaying pixel elements includes a capacitance elementformed of a channel capacitance as a pixel data holding element.
 11. Theimage display device according to claim 10, further comprising: acircuit for supplying a boost signal to said capacitance element. 12.The image display device according to claim 1, further comprising:transfer circuitry for externally transferring an output signal of theamplifier circuit in a test operation mode.
 13. The image display deviceaccording to claim 12, wherein said transfer circuitry includes: a testoutput circuit for externally outputting received data, and a selectcircuit for sequentially selecting and coupling the output signals ofthe amplifier circuits to said test output circuit.